The present invention relates to an interconnection board, a semiconductor device having an interconnection board, a method of forming the interconnection board and a method of mounting the semiconductor chip on the interconnection board, and more particularly to a multilayer interconnection board for allowing a flip-chip semiconductor chip to be mounted thereon, a semiconductor device having a multilayer interconnection board, a method of forming the multilayer interconnection board and a method of mounting the flip-chip semiconductor chip on the multilayer interconnection board.
In recent years, the importance of the flip-chip semiconductor chip for realizing the high density package has been on the increase. FIG. 1 is a schematic cross sectional elevation view illustrative of a flip-chip semiconductor chip. A flip-chip semiconductor chip 101 has a first surface which further has a predetermined area array of external terminals not illustrated on a peripheral area thereof and/or an active region thereof. Bumps 102 are provided on the external terminals. The bumps 102 are made of a metal material such as a solder material, Au, Sn—Ag based alloy. FIG. 2 is a schematic cross sectional elevation view illustrative of a flip-chip semiconductor chip mounted on a multilayer interconnection board. A multilayer interconnection board 103 has electrode pads which patterns correspond to patterns of the bumps 102 of the flip-chip semiconductor chip 101. The flip-chip semiconductor chip 101 is mounted on the multilayer interconnection board 103. If the bumps 102 are made of a solder material, an IR re-flow process using a flux is used for mounting the flip-chip semiconductor chip 101 on the multilayer interconnection board 103. The multilayer interconnection board 103 mounted with the flip-chip semiconductor chip 101 is further mounted on a circuit board through external terminals which are not illustrated.
The multilayer interconnection board 103 is different in linear expansion coefficient from the flip-chip semiconductor chip 101. The above conventional technique is disadvantageous in deteriorated mounting reliability, particularly deteriorated temperature cycle characteristics. In order to solve the above disadvantage, the following two conventional techniques have been proposed.
The first technique is to use, for the multilayer interconnection board, a ceramic-based material having a small difference in linear expansion coefficient from silicon of the flip-chip semiconductor chip 101. The use of the ceramic-based material is effective in improvement in reliability of mounting the flip-chip semiconductor chip 101 on the multilayer interconnection board 103, but disadvantageous as the ceramic-based material is expensive. The application of this conventional technique is limited to supercomputers and large scale computers.
The second technique is to use, for the multilayer interconnection board, an organic material which is inexpensive but is larger in linear expansion coefficient than silicon of the flip-chip semiconductor chip. In this second technique, an under-fill resin is provided between the semiconductor chip and the multilayer interconnection board, so that a shearing stress of the bumps between the semiconductor chip and the multilayer interconnection board is distributed or dispersed to the under-fill resin which covers the bumps, thereby to improve the reliability.
If the second technique using the organic material for the multilayer interconnection board is selected, then the multilayer interconnection board may be a build-up board in view of a minimum pitch of bump array patterns and the number of pins. FIGS. 3A through 3F are fragmentary cross sectional elevation views illustrative of build-up boards as the multilayer interconnection boards in sequential steps involved in a conventional fabrication method.
With reference to FIG. 3A, a glass epoxy base material board 104, typically FR4, FR5 or BT board, is prepared. Cu-foils 105 having a thickness in the range of 10–40 micrometers are adhered on both surfaces of the glass epoxy base material board 104. The Cu-foils 105 are then patterned to form Cu-interconnection patterns 105 on both surfaces of the glass epoxy base material board 104. A penetrating hole is made to the glass epoxy base material board 104 by a drilling process and then the penetrating hole is then plated thereby to form a plated through hole 106 which penetrates the glass epoxy base material board 104 and electrically connecting the Cu-interconnection patterns 105. An insulative resin filler is filled to the plated through hole 106, whereby a core board 107 is completed.
With reference to FIG. 3B, insulating resin material layers 108 are formed over the both surfaces of the glass epoxy base material board 104 so that the insulating resin material layers 108 cover the Cu-interconnection patterns 105. An opening 109 is selectively formed in the insulating resin material layers 108 by a photo-lithography technique or a laser beam process, so that a part of the Cu-interconnection patterns 105 is shown through the opening 109.
With reference to FIG. 3C, metal thin film layers 110 are entirely formed by a sputtering method or a Cu-electroless plating process, so that the metal thin film layers 110 extend on the insulating resin material layers 108 and in the opening 109, whereby the metal thin film layers 110 are electrically connected with the Cu-interconnection patterns 105.
With reference to FIG. 3D, photo-resist films 111 having a thickness in the range of 20–40 micrometers or dry films are formed over the metal thin film layers 110. The photo-resist films 111 or the dry films are patterned by exposure and subsequent development processes thereby to form photo-resist patterns 111 or dry film patterns on the metal thin film layers 110.
With reference to FIG. 3E, a selective Cu-electroplating process is carried out by use of the photo-resist patterns 111 or the dry film patterns as masks and also use of the metal thin film layers 110 as an electric supply line, thereby to selectively form interconnection patterns 112.
With reference to FIG. 3F, the photo-resist patterns 111 or the dry film patterns are removed. A selective wet etching process to the metal thin film layers 110 is carried out by use of the interconnection patterns 112 as a mask for selectively removing the metal thin film layers 110 to complete the interconnection patterns 112.
If necessary, the above processes shown in FIGS. 3B through 3F will be repeated to increase the number of the multilayers or the multilevels of the interconnections to complete the build-up board or the multilayer interconnection board.
The above second conventional technique using the organic material for the multilayer interconnection board is advantages in selecting the glass epoxy resin base material which is inexpensive and superior in formability of through holes. However, the glass epoxy resin base material has a large difference in thermal expansion coefficient from the semiconductor chip, whereby a large stress is applied between the multilayer interconnection board of the glass epoxy resin base material and the semiconductor chip thereby to drop the reliability in connection between the multilayer interconnection board and the semiconductor chip. The above multilevel interconnection patterns 105 and 112 over the glass epoxy base material board 104 are so thick as to relax the stress applied between the multilayer interconnection board and the semiconductor chip due to the relatively large thermal expansion coefficient between the multilayer interconnection board and the semiconductor chip. The necessary thickness of the above multilevel interconnection patterns 105 and 112 is, for example, in the range of 10–30 micrometers. This further requires that the thickness of the photo-resist patterns 111 or the dry film patterns is, for example, in the range of 20–40 micrometers. As a result, the minimum pitch of the photo-resist patterns 111 or the dry film is about 30 micrometers. Accordingly, the minimum pitch of the above multilevel interconnection patterns 105 and 112 is about 30 micrometers. This limitation to minimize the pitch of the above multilevel interconnection patterns makes it difficult to further increase the density of the multilayer interconnection board and further reduce the external size of the multilayer interconnection board.
Consequently, the multilayer interconnection board of the glass epoxy resin base material makes it difficult to further increase the density of the multilayer interconnection board and further reduce the external size of the multilayer interconnection board. Even the glass epoxy resin base material is inexpensive, the number of the multilayer interconnection boards obtained from a single large panel is small. This makes it difficult to further reduce the cost of the multilayer interconnection board.
Further, when the insulating resin material layers 108 are formed over the both surfaces of the glass epoxy base material board 104, the multilayer interconnection board is likely to be bent.
Furthermore, when the multilayer interconnection board with the semiconductor chip is mounted on a circuit board, a stress is applied between the multilayer interconnection board and the circuit board due to a difference in thermal expansion coefficient between the multilayer interconnection board and the circuit board, thereby deteriorating a reliability in connection between the multilayer interconnection board and the circuit board.
In the above circumstances, it had been required to develop a novel multilayer interconnection board free from the above problems, as well as a semiconductor device having the novel interconnection board.